US 12,125,706 B2
Semiconductor device and method of manufacture
Chun-Yen Peng, Hsinchu (TW); Te-Yang Lai, Hsinchu (TW); Sai-Hooi Yeong, Zhubei (TW); and Chi On Chui, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 8, 2023, as Appl. No. 18/331,387.
Application 18/331,387 is a continuation of application No. 17/403,263, filed on Aug. 16, 2021, granted, now 11,710,665.
Application 17/403,263 is a continuation of application No. 16/549,536, filed on Aug. 23, 2019, granted, now 11,101,180, issued on Aug. 24, 2021.
Prior Publication US 2023/0317524 A1, Oct. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/3115 (2006.01); H01L 21/8234 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/28185 (2013.01) [H01L 21/02356 (2013.01); H01L 21/28158 (2013.01); H01L 21/3115 (2013.01); H01L 21/823431 (2013.01); H01L 21/823462 (2013.01); H01L 29/517 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a gate dielectric layer over a top surface and sidewalls of a semiconductor fin, wherein the gate dielectric layer comprises a plurality of nano-crystallite regions suspended within an amorphous matrix material, wherein the amorphous matrix material separates grain boundaries of the plurality of nano-crystallite regions, and wherein the plurality of nano-crystallite regions have a first crystalline phase;
performing a first anneal process to modify the first crystalline phase of the plurality of nano-crystallite regions to a second crystalline phase that is different from the first crystalline phase;
forming a capping layer over the gate dielectric layer after the first anneal process; and
performing a second anneal process to further crystallize the plurality of nano-crystallite regions.