US 12,125,697 B2
Integrated method for low-cost wide band gap semiconductor device manufacturing
Tirunelveli Subramaniam Ravi, San Jose, CA (US); and Bishnu Gogoi, Scottsdale, AZ (US)
Assigned to ThinSiC Inc., Santa Clara, CA (US)
Filed by ThinSiC Inc., Santa Clara, CA (US)
Filed on Nov. 2, 2023, as Appl. No. 18/386,571.
Application 18/386,571 is a continuation of application No. 17/533,516, filed on Nov. 23, 2021, granted, now 11,848,197.
Claims priority of provisional application 63/119,541, filed on Nov. 30, 2020.
Prior Publication US 2024/0063013 A1, Feb. 22, 2024
Int. Cl. H01L 21/02 (2006.01)
CPC H01L 21/02019 (2013.01) [H01L 21/02271 (2013.01); H01L 21/02389 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method of forming a plurality of semiconductor devices overlying a substrate that can be used two or more times comprising:
providing the substrate comprising gallium nitride (GaN) or silicon carbide (SiC);
forming a merge layer in or below an entire surface of the substrate wherein the merge layer is configured to provide a surface that comprises a majority surface of merged epitaxial lateral overgrowth (MELO);
forming an exfoliation layer in or below the surface of the substrate;
growing one or more device layers in an epitaxial reactor overlying the merge layer wherein the one or more device layers are formed by vertical epitaxy;
forming the plurality of semiconductor devices wherein the substrate is configured to separate from the merge layer at the exfoliation layer; and
polishing a surface of the substrate after exfoliation to prepare the substrate for reuse.