US 12,125,683 B2
Method to improve wafer edge uniformity
Mingle Tong, Sunnyvale, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on May 19, 2021, as Appl. No. 17/324,435.
Prior Publication US 2022/0375727 A1, Nov. 24, 2022
Int. Cl. H01J 37/32 (2006.01); C23C 14/54 (2006.01); C23C 16/52 (2006.01); H01L 21/02 (2006.01); H01L 21/033 (2006.01); H01L 21/66 (2006.01)
CPC H01J 37/32495 (2013.01) [C23C 14/545 (2013.01); C23C 16/52 (2013.01); H01J 37/32715 (2013.01); H01J 37/32899 (2013.01); H01L 21/02274 (2013.01); H01L 21/0332 (2013.01); H01L 22/26 (2013.01); H01J 2237/3321 (2013.01); H01J 2237/3323 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor processing system, comprising:
a chamber body comprising sidewalls and a base;
a substrate support extending through the base of the chamber body, wherein the substrate support comprises:
a support plate; and
a shaft coupled with the support plate; and
a liner positioned within the chamber body and positioned radially outward of a peripheral edge of the support plate, wherein:
an inner surface of the liner comprises an emissivity texture, wherein the emissivity texture comprises a laser-textured pattern, the laser-textured pattern comprising etched and non-etch portions of the inner surface of the liner.