US 12,125,618 B2
Chip component production method
Yasushi Akahane, Nagano (JP); and Nobuhiko Tamada, Nagano (JP)
Assigned to KOA CORPORATION, Nagano (JP)
Appl. No. 17/769,311
Filed by KOA CORPORATION, Nagano (JP)
PCT Filed Sep. 24, 2020, PCT No. PCT/JP2020/036055
§ 371(c)(1), (2) Date Apr. 14, 2022,
PCT Pub. No. WO2021/075222, PCT Pub. Date Apr. 22, 2021.
Claims priority of application No. 2019-191456 (JP), filed on Oct. 18, 2019.
Prior Publication US 2024/0153678 A1, May 9, 2024
Int. Cl. H01C 17/00 (2006.01); C25D 3/56 (2006.01); C25D 5/12 (2006.01); C25D 7/06 (2006.01); C25D 21/12 (2006.01); H01C 1/032 (2006.01); H01C 1/142 (2006.01); H01C 17/242 (2006.01)
CPC H01C 17/006 (2013.01) [C25D 3/562 (2013.01); C25D 5/12 (2013.01); C25D 7/0642 (2013.01); C25D 21/12 (2013.01); H01C 1/032 (2013.01); H01C 1/142 (2013.01); H01C 17/242 (2013.01)] 2 Claims
OG exemplary drawing
 
1. A chip component production method comprising the steps of:
forming a functional element on a component main body;
forming a pair of internal electrodes to cover both end portions of the component main body;
forming a barrier layer including nickel as a main component and containing phosphorus on a surface of each of the pair of internal electrodes by electrolytic plating; and
forming an external connection layer mainly composed of tin on a surface of the barrier layer by electrolytic plating, wherein
the step of forming the barrier layer by electrolytic plating includes a step of changing a current density with time so as to make a content rate of phosphorus in an inner region adjacent to each of the pair of the internal electrodes different from that in an outer region adjacent to the external connection layer.