US 12,125,551 B2
Structure for multiple sense amplifiers of memory device
Ku-Feng Lin, New Taipei (TW); and Hiroki Noguchi, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jul. 27, 2022, as Appl. No. 17/874,973.
Application 17/874,973 is a continuation of application No. 16/943,345, filed on Jul. 30, 2020, granted, now 11,450,357.
Claims priority of provisional application 62/928,030, filed on Oct. 30, 2019.
Prior Publication US 2022/0358973 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 7/06 (2006.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01)
CPC G11C 7/062 (2013.01) [G11C 11/16 (2013.01); G11C 13/004 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of sense amplifiers;
a plurality of memory cells coupled to a plurality of first inputs of the plurality of sense amplifiers respectively;
a plurality of data lines coupled to a plurality of second inputs of the plurality of sense amplifiers respectively;
a plurality of reference cells arranged in a plurality of columns respectively and coupled to the plurality of data lines respectively, wherein the plurality of reference cells comprises a plurality of resistive elements,
wherein a first number of the resistive elements that have a first resistance and are ones, in the plurality of columns, closest to the plurality of sense amplifiers is different from a second number of the resistive elements that have a second resistance and are ones, in the plurality of columns, closest to the plurality of sense amplifiers, the first and second resistances being different from each other; and
a connection line coupled to the plurality of data lines,
wherein in a read mode, one of the plurality of sense amplifiers is configured to access the plurality of resistive elements arranged in one of the plurality of columns.