	US 12,125,548 B2
	Memory array test method and system
Chien-Hao Huang, Hsinchu (TW); Katherine H. Chiang, Hsinchu (TW); Cheng-Yi Wu, Hsinchu (TW); and Chung-Te Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 25, 2023, as Appl. No. 18/358,202.
Application 18/358,202 is a continuation of application No. 17/884,634, filed on Aug. 10, 2022, granted, now 11,715,546.
Application 17/884,634 is a continuation of application No. 17/175,027, filed on Feb. 12, 2021, granted, now 11,450,399, issued on Sep. 20, 2022.
Claims priority of provisional application 63/031,185, filed on May 28, 2020.
Prior Publication US 2023/0377670 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/00 (2006.01); G11C 11/16 (2006.01); G11C 29/38 (2006.01)

CPC G11C 29/38 (2013.01) [G11C 11/1673 (2013.01); G11C 11/1675 (2013.01)]

20 Claims

1. A method of testing a non-volatile memory (NVM) array, the method comprising:

heating the NVM array to a target temperature;

while the NVM array is heated to the target temperature:

programming a subset of NVM cells of the NVM array to first resistance levels and obtaining a first current distribution;

programming the subset of NVM cells to second resistance levels and obtaining a second current distribution;

calculating a current threshold level from the first and second current distributions; and

for each NVM cell of the NVM array:

programing the NVM cell to one of the first or second resistance levels; and

using the current threshold level to determine a first pass/fail (P/F) status and a second P/F status at the programmed resistance level; and

calculating a bit error rate (BER) of the NVM array based on the first and second current distributions and the first and second P/F status of each NVM cell of the NVM array.