US 12,125,540 B2
Write latency and energy using asymmetric cell design
Mattia Robustelli, Milan (IT); and Innocenzo Tortorelli, Cernusco Sul Naviglio (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 29, 2022, as Appl. No. 17/733,474.
Prior Publication US 2023/0352095 A1, Nov. 2, 2023
Int. Cl. G11C 16/10 (2006.01); G11C 16/22 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/22 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); G11C 16/3404 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method by a memory device, comprising:
receiving, at the memory device, a command to write a first logic state to a first subset of a set of memory cells and a second logic state to a second subset of the set of memory cells, wherein each memory cell of the set of memory cells is coupled with a first access line via a first electrode having a first contact area and is coupled with a respective second access line via a second electrode having a second contact area different than the first contact area;
applying, during a first duration and in response to the command, a first voltage to the first access line, wherein, during the first duration, at least one memory cell of the second subset thresholds and at least one memory cell of the first subset is written to the first logic state based at least in part on applying the first voltage to the first access line, the thresholding based at least in part on the second contact area being different than the first contact area; and
applying, during a second duration after the first duration and in response to the command, a second voltage to the first access line, wherein, during the second duration, the at least one memory cell of the second subset is written to the second logic state based at least in part on applying the second voltage to the first access line.