| CPC G11C 11/412 (2013.01) [G11C 11/419 (2013.01); H10B 10/12 (2023.02)] | 20 Claims |
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1. A memory device, comprising:
a first conductive segment configured to receive a first reference voltage signal;
a first row of memory cells coupled to a first word line;
a second row of memory cells coupled to a second word line different from the first word line,
wherein the first row of memory cells comprises:
a first memory cell coupled to the first conductive segment to receive the first reference voltage signal; and
a second memory cell, and wherein the second row of memory cells comprises:
a third memory cell coupled to the first conductive segment to receive the first reference voltage signal, wherein the first memory cell and the third memory cell share the first conductive segment, and the third memory cell is arranged between the first memory cell and the second memory cell;
a fourth memory cell, wherein the second memory cell is arranged between the third memory cell and the fourth memory cell; and
a second conductive segment extending in a first direction, and configured to couple the first memory cell and the third memory cell to the first conductive segment,
wherein the first conductive segment extends in a second direction different from the first direction.
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