US 12,125,513 B2
System on chip (SOC) with processor and integrated ferroelectric memory
Jon D. Trantham, Chanhassen, MN (US); Praveen Viraraghavan, Chicago, IL (US); John W. Dykes, Eden Prairie, MN (US); Ian J. Gilbert, Chanhassen, MN (US); Sangita Shreedharan Kalarickal, Eden Prairie, MN (US); Matthew J. Totin, Excelsior, MN (US); Mohamad El-Batal, Superior, CO (US); and Darshana H. Mehta, Shakopee, MN (US)
Assigned to SEAGATE TECHNOLOGY LLC, Fremont, CA (US)
Filed by Seagate Technology LLC, Fremont, CA (US)
Filed on Apr. 22, 2022, as Appl. No. 17/726,864.
Claims priority of provisional application 63/201,285, filed on Apr. 22, 2021.
Prior Publication US 2022/0343962 A1, Oct. 27, 2022
Int. Cl. G11C 11/22 (2006.01); G11C 7/10 (2006.01); G11C 17/12 (2006.01)
CPC G11C 11/2273 (2013.01) [G11C 7/1039 (2013.01); G11C 11/2275 (2013.01); G11C 11/2297 (2013.01); G11C 17/12 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system on chip (SOC) integrated circuit device, comprising:
a processor circuit;
a ferroelectric memory formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer;
a read/write circuit configured to write data to the FMEs and to subsequently read back data from the FMEs responsive to respective write and read signals supplied by the processor circuit; and
a refresh circuit configured to selectively refresh the FMEs in a first mode and to not refresh the FMEs in a second mode responsive to a mode selection signal from the processor circuit, wherein the refresh circuit is further configured to receive an inhibit signal in the second mode and in response to receiving the inhibit signal disable the refresh the FMEs.