US 12,125,122 B2
Fault detection in a real-time image pipeline
Mihir Narendra Mody, Bengaluru (IN); Niraj Nandan, Plano, TX (US); Ankur Ankur, New Delhi (IN); Mayank Mangla, Allen, TX (US); and Prithvi Shankar Yeyyadi Anantha, Bengaluru (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Dec. 20, 2021, as Appl. No. 17/556,161.
Prior Publication US 2023/0196497 A1, Jun. 22, 2023
Int. Cl. G06T 1/20 (2006.01); G06F 9/48 (2006.01); G06F 11/10 (2006.01); G06T 1/60 (2006.01)
CPC G06T 1/20 (2013.01) [G06F 9/4812 (2013.01); G06F 11/1004 (2013.01); G06T 1/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
an image signal processor including an image processing pipeline; and
a scheduler module configured to:
determine that the image processing pipeline has begun processing image data;
based on determining that the image processing pipeline has begun processing the image data, cause the image processing pipeline to receive first configuration information associated with testing the image processing pipeline; and
during a blanking period of the image data,
stop the image processing pipeline from processing the image data;
cause the image processing pipeline to process test data based on the first configuration information;
receive a first indication to stop the image processing pipeline from processing the test data;
determine whether the image processing pipeline would have completed processing the test data when stopping the image processing pipeline from processing the test data; and
based on determining that the image processing pipeline would not have completed processing the test data, generate a second indication that processing of the test data is not completed.