US 12,124,944 B2
Precise data tuning method and apparatus for analog neural memory in an artificial neural network
Hieu Van Tran, San Jose, CA (US); Steven Lemke, Boulder Creek, CA (US); Nhan Do, Saratoga, CA (US); and Mark Reiten, Alamo, CA (US)
Assigned to SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US)
Filed on Feb. 25, 2021, as Appl. No. 17/185,725.
Application 17/185,725 is a continuation in part of application No. 16/829,757, filed on Mar. 25, 2020, granted, now 11,636,322.
Claims priority of provisional application 62/957,013, filed on Jan. 3, 2020.
Prior Publication US 2021/0209458 A1, Jul. 8, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 3/065 (2023.01); G06F 17/16 (2006.01)
CPC G06N 3/065 (2023.01) [G06F 17/16 (2013.01)] 48 Claims
OG exemplary drawing
 
1. A system comprising:
a vector-by-matrix multiplication array of non-volatile memory cells, wherein a weight value w is stored as a differential pair w+ and w− in a first non-volatile memory cell and a second non-volatile memory cell in the array according to the formula w=(w+)−(w−), where w+ includes a non-zero offset value and w− includes the non-zero offset value.