US 12,124,847 B2
Systems, methods, and apparatuses for tile transpose
Robert Valentine, Kiryat Tivon (IL); Dan Baum, Haifa (IL); Zeev Sperber, Zichron Yaakov (IL); Jesus Corbal, Barcelona (ES); Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US); Bret L Toll, Hillsboro, OR (US); Mark J. Charney, Lexington, MA (US); Barukh Ziv, Haifa (IL); Alexander Heinecke, San Jose, CA (US); Milind Girkar, Sunnyvale, CA (US); Menachem Adelman, Haifa (IL); and Simon Rubanovich, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 16/474,475
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Jul. 1, 2017, PCT No. PCT/US2017/040536
§ 371(c)(1), (2) Date Jun. 27, 2019,
PCT Pub. No. WO2018/174926, PCT Pub. Date Sep. 27, 2018.
Claims priority of provisional application 62/473,732, filed on Mar. 20, 2017.
Prior Publication US 2019/0347100 A1, Nov. 14, 2019
Int. Cl. G06F 9/30 (2018.01); G06F 7/485 (2006.01); G06F 7/487 (2006.01); G06F 7/76 (2006.01); G06F 9/38 (2018.01); G06F 17/16 (2006.01)
CPC G06F 9/30036 (2013.01) [G06F 7/485 (2013.01); G06F 7/4876 (2013.01); G06F 7/762 (2013.01); G06F 9/3001 (2013.01); G06F 9/30032 (2013.01); G06F 9/30043 (2013.01); G06F 9/30109 (2013.01); G06F 9/30112 (2013.01); G06F 9/30134 (2013.01); G06F 9/30145 (2013.01); G06F 9/30149 (2013.01); G06F 9/3016 (2013.01); G06F 9/30185 (2013.01); G06F 9/30196 (2013.01); G06F 9/3818 (2013.01); G06F 9/3836 (2013.01); G06F 17/16 (2013.01); G06F 2212/454 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A processor comprising:
decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier of a single two-dimensional tile register in a matrix operations accelerator of the processor, and a destination matrix operand identifier; and
execution circuitry to execute the decoded instruction to cause the matrix operations accelerator to transpose each row of elements of the identified source matrix operand into a corresponding column of the identified destination matrix operand and zero any remaining columns of the identified destination matrix operand and unconfigured rows of the identified destination matrix operand.