US 12,124,785 B2
Method of making cell regions of integrated circuits
Jia-Hong Gao, Hsinchu (TW); and Hui-Zhong Zhuang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/448,115.
Application 18/448,115 is a division of application No. 17/405,626, filed on Aug. 18, 2021.
Prior Publication US 2023/0409798 A1, Dec. 21, 2023
Int. Cl. G06F 30/30 (2020.01); G06F 30/392 (2020.01); H01L 21/04 (2006.01); H01L 27/02 (2006.01)
CPC G06F 30/392 (2020.01) [H01L 21/041 (2013.01); H01L 27/0207 (2013.01)] 20 Claims
OG exemplary drawing
 
5. A method of manufacturing an integrated circuit (IC), the method comprising:
forming a first active region in a first cell;
forming a plurality of second active regions in a second cell, wherein the second cell abuts the first cell;
forming a third active region in a third cell, wherein the third cell abuts the second cell, the second cell is between the first cell and the third cell, and a height of the second cell is different from a height of the first cell or the third cell;
forming a plurality of gate structures extending across each of the first active region, the plurality of second active regions, and the third active region; and
removing a first portion of a first gate structure of the plurality of gate structures at an interface between the first cell and the second cell, wherein the first portion of the first gate structure is between the first active region and the plurality of second active regions.