US 12,124,739 B2
Memory devices including idle time prediction
Tyler L. Betz, Meridian, ID (US); Sundararajan N. Sankaranarayanan, Fremont, CA (US); Roberto Izzi, Caserta (IT); Massimo Zucchinali, Torre Boldone (IT); and Xiangyu Tang, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Sep. 21, 2022, as Appl. No. 17/949,333.
Claims priority of provisional application 63/402,186, filed on Aug. 30, 2022.
Prior Publication US 2024/0069809 A1, Feb. 29, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0634 (2013.01); G06F 3/0679 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A memory device comprising:
an interface to communicate with a host;
an array of memory cells; and
a controller configured to access the array of memory cells in response to commands from the host,
wherein the controller is further configured to:
enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response to receiving a second command from the host;
for a plurality of idle times, generate a history indicating a length of each idle time; and
predict the length of a subsequent idle time based on the history;
wherein the controller is further configured to, in response to predicting the length of the subsequent idle time will be less than a first threshold time:
in response to a subsequent first command, transition to a first power state;
transition to a second power state higher than the first power state in response to the first threshold time elapsing;
run background operations in the second power state; and
in response to completing the background operations, transition to a third power state lower than the first power state.