US 12,124,713 B2
System-on-chip comprising a non-volatile memory
Francesco Bombaci, Messina (IT); and Andrea Tosoni, Brignoles (FR)
Assigned to STMICROELECTRONICS S.r.l., Agrate Brianza (IT); and STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR)
Filed by STMICROELECTRONICS S.r.l., Agrate Brianza (IT); and STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR)
Filed on Nov. 21, 2022, as Appl. No. 18/057,390.
Claims priority of application No. 2112807 (FR), filed on Dec. 1, 2021.
Prior Publication US 2023/0168821 A1, Jun. 1, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0629 (2013.01) [G06F 3/0622 (2013.01); G06F 3/0665 (2013.01); G06F 3/0679 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system-on-a-chip comprising:
a processor, which, in operation, generates memory access requests;
a memory including one or more physical banks divided into a succession of sectors, each sector having a size equal to a smallest erasable size of the memory; and
a memory interface coupled to the memory and to the processor, the memory interface including one or more configuration registers, wherein the memory interface, in operation:
in response to receiving memory configuration information, stores logical memory bank configuration information in the one or more configuration registers, the logical memory bank configuration information assigning each sector of the one or more physical banks of the memory to a respective logical memory bank of a plurality of logical memory banks; and
in response to receiving a memory access request from the processor, controls access to the memory based on the logical memory bank configuration information stored in the one or more configuration registers, wherein,
the memory interface defines the plurality of logical memory banks at different addresses, and
the stored logical memory bank configuration information defines a first logical memory bank to store compiled code of an application and a second logical memory bank to store an updated version of the compiled code of the application, the first and second logical memory banks having an equal number of assigned memory sectors and being interchangeable.