US 12,124,403 B2
Systems and methods for multi-architecture computing
Eliezer Tamir, Jerusalem (IL); and Ben-Zion Friedman, Jerusalem (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 14, 2022, as Appl. No. 17/693,696.
Application 17/693,696 is a continuation of application No. 15/584,343, filed on May 2, 2017, granted, now 11,275,709.
Prior Publication US 2022/0197851 A1, Jun. 23, 2022
Int. Cl. G06F 15/173 (2006.01); G06F 9/455 (2018.01); G06F 9/48 (2006.01); G06F 11/14 (2006.01); G06F 11/30 (2006.01); G06F 15/76 (2006.01); H04L 67/1001 (2022.01)
CPC G06F 15/17325 (2013.01) [G06F 9/4856 (2013.01); G06F 11/14 (2013.01); G06F 11/3006 (2013.01); G06F 11/3041 (2013.01); G06F 11/3055 (2013.01); G06F 11/3058 (2013.01); G06F 11/3062 (2013.01); G06F 15/76 (2013.01); G06F 9/4552 (2013.01); G06F 2201/815 (2013.01); G06F 2201/84 (2013.01); H04L 67/1001 (2022.05)] 21 Claims
OG exemplary drawing
 
1. A computed implemented method, comprising:
executing a program as a first binary representation on a first core having a first instruction set architecture (ISA);
suspending execution of the program; and
resuming execution of the program, comprising executing a second binary representation of the program on a second core having a second ISA different from the first ISA.