US 12,124,379 B2
Management circuitry for a least recently used memory management process
Karthik Thucanakkenpalayam Sundararajan, Fremont, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Oct. 6, 2022, as Appl. No. 17/961,473.
Prior Publication US 2024/0119007 A1, Apr. 11, 2024
Int. Cl. G06F 12/0891 (2016.01)
CPC G06F 12/0891 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving an accessed memory element, the accessed memory element requested by a processor from a memory;
comparing, via memory management circuitry, the accessed memory element to stored elements within the memory to generate control signals;
generating, via gate control circuitry, gate control signals, wherein a second gate control signal of the gate control signals is generated from a comparison of a first control signal of the control signals and a second control signal of the control signals; and
updating an order of the stored elements within frames of the memory by updating a first frame of the frames based on a first gate control signal of the gate control signals and a second frame of the frames based on the second gate control signal, wherein the first gate control signal is a pass through version of the first control signal.