US 12,124,347 B2
System and method for managing secure memories in integrated circuits
Neha Srivastava, New Delhi (IN); Gautam Tikoo, Noida (IN); and Harshit Saxena, Faizabad (IN)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Jan. 11, 2023, as Appl. No. 18/152,797.
Claims priority of application No. 202221065262 (IN), filed on Nov. 15, 2022.
Prior Publication US 2024/0160545 A1, May 16, 2024
Int. Cl. G06F 11/27 (2006.01); G06F 12/14 (2006.01)
CPC G06F 11/27 (2013.01) [G06F 12/14 (2013.01); G06F 2212/1052 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
a first secure memory element and a second secure memory element that are configured to store identical security-related data; and
a memory management system that is coupled to the first secure memory element and the second secure memory element, and configured to:
execute a first memory operation on the first secure memory element, wherein the first memory operation facilitates execution of a security operation based on the security-related data stored in the first secure memory element;
execute, while the first memory operation is being executed on the first secure memory element, a control operation on the second secure memory element, wherein the control operation is associated with safety of the IC;
copy, after the execution of the first memory operation and the control operation, the data stored in the first secure memory element to the second secure memory element, and
execute a security operation based on the data copied in the second secure memory element and a control operation associated with safety of the IC on the first secure memory element after copying the data.