US 12,124,328 B2
Data processing system having a memory controller with inline error correction code (ECC) support
Diviya Jain, New Delhi (IN); and James Andrew Welker, Leander, TX (US)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Apr. 26, 2022, as Appl. No. 17/660,690.
Prior Publication US 2023/0342240 A1, Oct. 26, 2023
Int. Cl. G06F 11/10 (2006.01)
CPC G06F 11/1044 (2013.01) [G06F 2201/805 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller configured to receive access requests to access a memory, the memory controller comprising:
a transaction scheduler circuit having a scheduler queue, wherein for each received access request, the transaction scheduler circuit is configured to allocate a new entry in the scheduler queue, store an access address corresponding to the access request as a data address into the new entry, generate an error correction code (ECC) address from the data address and store the ECC address into the new entry, and set a corresponding ECC mode field in the new entry to indicate whether the data address or ECC address of the new entry is to be exposed during arbitration; and
a command queue, wherein the transaction scheduler circuit, during an arbitration cycle, is configured to select a transaction from the scheduler queue using an exposed address of each valid entry, and configured to provide the selected transaction to the command queue.