US 12,123,911 B1
Integrated circuit with timing correction circuitry
Shilpa Gupta, Rohini (IN); Rishi Bhooshan, Noida (IN); Anis Mahmoud Jarrar, Austin, TX (US); David Russell Tipple, Leander, TX (US); and Hadi Ahmadi Balef, Eindhoven (NL)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Jul. 19, 2023, as Appl. No. 18/354,925.
Claims priority of application No. 202311027607 (IN), filed on Apr. 14, 2023.
Int. Cl. G01R 31/28 (2006.01); G01R 31/317 (2006.01); G01R 31/3185 (2006.01); G01R 31/3193 (2006.01)
CPC G01R 31/318525 (2013.01) [G01R 31/31727 (2013.01); G01R 31/31932 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a critical data path including a flip flop configured to receive a data input and provide a latched data output;
a margin sensing circuit coupled to the flip flop, comprising:
a delay generator configured to receive the data input and provide a plurality of delayed data outputs wherein the plurality of delayed data outputs correspond to delayed versions of the data input with increasing amounts of delay;
a selector circuit configured to select a delayed data output of the plurality of delayed data outputs based on a set of select signals, and having an output;
a shadow latch corresponding to the flip flop, having an input coupled to the output of the selector circuit and configured to latch a value at its input to provide as a latched shadow output;
a comparator circuit configured to provide a match error indicator based on a comparison between the latched data output from the flip flop and the latched shadow output from the shadow latch; and
an error latch configured to latch an error value based at least on the match error indicator and to provide the latched error value as an error indicator; and
a correcting circuit coupled to the margin sensing circuit and the flip flop, comprising:
a clock delay generator configured to receive a clock and provide a plurality of delayed clocks wherein the plurality of delayed clocks correspond to delayed versions of the clock with increasing amounts of delay; and
a clock selector circuit configured to select a delayed clock of the plurality of delayed clocks based on a set of clock select signals, wherein each of the flip flop and the shadow latch are clocked by the selected delayed clock.