US 12,123,909 B2
Array of unit cells having pad structures
Yu-Ching Chiu, Hsinchu (TW); Chih-Feng Ku, Hsinchu (TW); and Chih-Kuang Kao, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 13, 2022, as Appl. No. 17/719,557.
Prior Publication US 2023/0333158 A1, Oct. 19, 2023
Int. Cl. G01R 31/317 (2006.01); G01R 31/3185 (2006.01); G06F 30/392 (2020.01); G06F 119/02 (2020.01)
CPC G01R 31/31717 (2013.01) [G01R 31/318533 (2013.01); G06F 30/392 (2020.01); G06F 2119/02 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
scanning a circuit layout;
identifying a plurality of layout regions of the circuit layout, wherein each of the plurality of layout regions is electrically coupled to a plurality of macro pad structures;
placing a plurality of unit cells in a layout region of the plurality of layout regions; and
forming a micro pad structure at a border of a unit cell of the plurality of unit cells, wherein the micro pad structure comprises interconnect structures that are electrically connected to the unit cell.