CPC H01L 29/0847 (2013.01) [H01L 23/528 (2013.01); H01L 28/60 (2013.01); H01L 29/1033 (2013.01); H01L 29/42376 (2013.01); H10B 12/03 (2023.02); H10B 12/05 (2023.02); H10B 12/30 (2023.02); H10B 12/48 (2023.02); H10B 12/50 (2023.02); H10B 53/10 (2023.02); H10B 53/20 (2023.02); H10B 53/30 (2023.02); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/28035 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/32134 (2013.01); H01L 27/0688 (2013.01)] | 33 Claims |
1. A memory array, comprising:
vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; and
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another; and
a sense-line structure extending elevationally through the vertically-alternating tiers, individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers being electrically coupled to the elevationally-extending sense-line structure.
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