CPC H10N 70/245 (2023.02) [G11C 13/0011 (2013.01); H10N 70/063 (2023.02); H10N 70/8265 (2023.02); H10N 70/841 (2023.02); H10N 70/8613 (2023.02)] | 20 Claims |
1. A method for manufacturing a memory device, comprising:
forming a bottom electrode over a substrate;
forming a heat dispersion layer over the bottom electrode, wherein a bottommost surface of the heat dispersion layer is above a bottom surface of the bottom electrode;
forming a dielectric layer over the heat dispersion layer;
forming a top electrode over the dielectric layer; and
wherein the heat dispersion layer comprises a first dielectric material.
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