CPC H10N 70/24 (2023.02) [H10N 50/01 (2023.02); H10N 70/011 (2023.02); H10N 70/063 (2023.02); H10N 70/20 (2023.02); H10N 70/801 (2023.02); H10N 70/826 (2023.02)] | 20 Claims |
1. A memory device, comprising:
a bottom electrode;
a magnetic tunnel junction (MTJ) structure over the bottom electrode, the bottom electrode having a top surface extending past opposite sidewalls of the MTJ structure;
an inner spacer contacting the top surface of the bottom electrode and one of the opposite sidewalls of the MTJ structure; and
an outer spacer contacting an outer sidewall of the inner spacer, the outer spacer protruding from a top surface of the inner spacer by a step height, wherein the outer spacer has a bottom surface higher than the top surface of the bottom electrode.
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