	US 11,800,818 B2
	Top electrode last scheme for memory cell to prevent metal redeposit
Chung-Yen Chou, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 9, 2021, as Appl. No. 17/371,468.
Application 17/371,468 is a division of application No. 16/197,526, filed on Nov. 21, 2018, granted, now 11,088,323.
Claims priority of provisional application 62/724,698, filed on Aug. 30, 2018.
Prior Publication US 2021/0351349 A1, Nov. 11, 2021
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01)

CPC H10N 70/063 (2023.02) [H10B 63/30 (2023.02); H10N 70/021 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/8833 (2023.02); G11C 2213/52 (2013.01)]

20 Claims

1. A method for forming a memory device, the method comprising:

forming a memory cell stack over a substrate, wherein the memory cell stack comprises a bottom metal layer, a top metal layer, and a data storage layer disposed between the bottom metal layer and the top metal layer;

forming a first dielectric layer over the top metal layer;

forming a second dielectric layer over the first dielectric layer;

patterning the memory cell stack and the first and second dielectric layers such that sidewalls of the data storage layer, sidewalls of the top metal layer, sidewalls of the bottom metal layer, sidewalls of the first dielectric layer, and sidewalls of the second dielectric layer are substantially aligned and are slanted at a non-zero angle, wherein the memory cell stack has a first height and has a width that continuously increases along the first height from a top surface of the memory cell stack in a first direction towards the substrate; and

forming a top electrode over the top metal layer, wherein the top electrode has a second height and has a width that continuously decreases along the second height from a top surface of the top electrode in the first direction, wherein the second height is greater than the first height.