CPC H10N 50/01 (2023.02) [H10B 61/10 (2023.02); H10B 61/22 (2023.02); H10B 61/00 (2023.02); H10N 50/80 (2023.02)] | 20 Claims |
1. An integrated circuit, comprising:
a dielectric layer;
a memory device comprising:
a bottom electrode via in the dielectric layer, wherein the dielectric layer has a first portion extending along sidewalls of the bottom electrode via, a second portion extending laterally from the first portion, and a third portion;
a bottom electrode over the bottom electrode via;
a resistance switching element over the bottom electrode; and
a top electrode over the resistance switching element; and
a resistor over the third portion of the dielectric layer, wherein a thickness of the third portion of the dielectric layer is greater than a thickness of the second portion of the dielectric layer.
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