US 11,800,724 B2
MRAM memory cell layout for minimizing bitcell area
Harry-Hak-Lay Chuang, Hsinchu (TW); Wen-Chun You, Hsinchu (TW); Hung Cho Wang, Hsinchu (TW); and Yen-Yu Shih, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd.
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Dec. 27, 2021, as Appl. No. 17/562,949.
Application 17/562,949 is a division of application No. 16/893,010, filed on Jun. 4, 2020, granted, now 11,244,983.
Claims priority of provisional application 62/866,361, filed on Jun. 25, 2019.
Prior Publication US 2022/0123051 A1, Apr. 21, 2022
Int. Cl. H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01)
CPC H10B 61/22 (2023.02) [H10N 50/01 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An MRAM memory cell, comprising:
a substrate;
a transistor over the substrate and including:
a first source region;
a second source region;
a drain region between the first and second source regions;
at least one first channel region between the drain region and the first source region;
at least one second channel region between the drain region and the second source region;
a first gate structure overlying the at least one first channel region; and
a second gate structure overlying the at least one second channel region;
a magnetic tunnel junction overlying the transistor, wherein the drain region is coupled to the magnetic tunnel junction;
a first metal layer overlying the transistor; and
a second metal layer overlying the first metal layer, wherein the second and first metal layers are configured to couple a common source line signal to the first and second source regions and to first neighboring first and second source regions of a first neighboring transistor of a first neighboring MRAM memory cell; and
a third metal layer overlying the second metal layer, the third metal layer being configured to couple a word line signal to the first and second gate structures.