US 11,800,720 B2
Memory cell having a top electrode interconnect arranged laterally from a recess
Tzu-Yu Chen, Kaohsiung (TW); Kuo-Chi Tu, Hsin-Chu (TW); Sheng-Hung Shih, Hsinchu (TW); Wen-Ting Chu, Kaohsiung (TW); Chih-Hsiang Chang, Taichung (TW); and Fu-Chen Chang, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Nov. 17, 2021, as Appl. No. 17/528,611.
Application 17/528,611 is a continuation of application No. 16/663,952, filed on Oct. 25, 2019, granted, now 11,183,503.
Claims priority of provisional application 62/880,816, filed on Jul. 31, 2019.
Prior Publication US 2022/0077165 A1, Mar. 10, 2022
Int. Cl. H10B 53/00 (2023.01); G11C 11/22 (2006.01); H10B 53/10 (2023.01); H10B 53/30 (2023.01); H01L 49/02 (2006.01)
CPC H10B 53/00 (2023.02) [G11C 11/221 (2013.01); H01L 28/55 (2013.01); H01L 28/60 (2013.01); H10B 53/10 (2023.02); H10B 53/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a bottom electrode disposed over a substrate;
a data storage structure disposed on the bottom electrode and configured to store a data state;
a top electrode disposed on the data storage structure, wherein the top electrode has interior surfaces that are vertically below an upper surface of the top electrode and that form a recess within the upper surface of the top electrode;
a masking layer contacting a bottom of the recess and extending to over the upper surface of the top electrode; and
an interconnect extending through the masking layer and to the top electrode, wherein the interconnect has a bottommost surface that is laterally outside of the recess.
 
9. An integrated chip, comprising:
a lower insulating structure disposed over a lower dielectric structure and having sidewalls extending through the lower insulating structure to a lower interconnect;
a bottom electrode arranged along the sidewalls and an upper surface of the lower insulating structure;
a data storage structure disposed on the bottom electrode and configured to store a data state;
a top electrode disposed on the data storage structure;
a hard mask disposed on the top electrode, wherein the hard mask has a bottommost surface that is laterally between sidewalls of the top electrode and that is vertically below a lower surface of the top electrode; and
an interconnect extending through the hard mask and contacting the top electrode laterally outside of the bottommost surface of the top electrode, wherein the interconnect is disposed within an upper dielectric structure that is over the lower insulating structure and that extends to a top surface of the top electrode.
 
15. An integrated chip, comprising:
a bottom electrode arranged along sidewalls and an upper surface of a lower insulating structure over a substrate;
a data storage structure disposed on the bottom electrode and configured to store a data state;
a top electrode disposed on the data storage structure;
an interconnect disposed within an upper dielectric structure over the top electrode, a bottommost surface of the interconnect contacting the top electrode; and
wherein an imaginary horizontal line, which extends through the top electrode, intersects an interface between a sidewall of the bottom electrode and a sidewall of the data storage structure directly below the bottommost surface of the interconnect, the imaginary horizontal line being parallel to an upper surface of the substrate that faces the bottom electrode.