CPC H10B 20/20 (2023.02) [G11C 17/16 (2013.01); G11C 17/18 (2013.01)] | 20 Claims |
1. A one-time program (OTP) memory device, comprising:
a source-line arranged over a bottom dielectric layer;
a bit-line;
a channel isolation structure arranged directly between the source-line and the bit-line along a first direction;
a channel structure arranged between the source-line and the bit-line along the first direction and further arranged beside the channel isolation structure in a second direction perpendicular to the first direction;
a vertical gate electrode extending in the first direction from the bottom dielectric layer to the bit-line and arranged beside the channel isolation structure in the second direction; and
a gate dielectric layer arranged between the vertical gate electrode and the bit-line, the source-line, and the channel structure.
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