US 11,800,703 B2
Vertical fuse memory in one-time program memory cells
Sheng-Chih Lai, Hsinchu County (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Aug. 4, 2022, as Appl. No. 17/880,754.
Application 17/880,754 is a division of application No. 16/885,362, filed on May 28, 2020.
Claims priority of provisional application 62/948,908, filed on Dec. 17, 2019.
Prior Publication US 2022/0375949 A1, Nov. 24, 2022
Int. Cl. G11C 17/16 (2006.01); H10B 20/20 (2023.01); G11C 17/18 (2006.01)
CPC H10B 20/20 (2023.02) [G11C 17/16 (2013.01); G11C 17/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A one-time program (OTP) memory device, comprising:
a source-line arranged over a bottom dielectric layer;
a bit-line;
a channel isolation structure arranged directly between the source-line and the bit-line along a first direction;
a channel structure arranged between the source-line and the bit-line along the first direction and further arranged beside the channel isolation structure in a second direction perpendicular to the first direction;
a vertical gate electrode extending in the first direction from the bottom dielectric layer to the bit-line and arranged beside the channel isolation structure in the second direction; and
a gate dielectric layer arranged between the vertical gate electrode and the bit-line, the source-line, and the channel structure.