CPC H05K 7/20509 (2013.01) [F25D 19/006 (2013.01); F28F 21/08 (2013.01); H01L 23/3738 (2013.01); H05K 7/20372 (2013.01); H05K 7/20481 (2013.01); H10N 60/10 (2023.02); F28F 2013/006 (2013.01)] | 16 Claims |
1. A thermalization arrangement at cryogenic temperatures, wherein the arrangement comprises a dielectric substrate layer on which substrate a device/s or component/s are positionable, and a heat sink component attached on another side of the substrate, the arrangement further comprising a conductive layer between the substrate layer and the heat sink component, a joint between the substrate layer and the conductive layer having minimal phonon thermal boundary resistance, and in which energy of conductive layer phonons are arranged to be absorbed by electrons, and another joint between the conductive layer and the heat sink component being electrically conductive, wherein the conductive layer is degenerately doped silicon.
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