CPC H04W 52/0216 (2013.01) [H04W 52/0229 (2013.01); H04L 67/12 (2013.01); H04W 84/12 (2013.01); Y02D 30/70 (2020.08)] | 20 Claims |
1. A circuit comprising:
a controller configured to:
receive a first decoded beacon frame which includes a first indication of a first data transmission;
receive a second decoded beacon frame which includes a second indication of a second data transmission;
compare the first and second decoded beacon frames to determine common bytes in the first and second decoded beacon frames;
determine an expected time of receiving the common bytes in a third beacon frame;
control a device to enter into a low power mode; and
control the device to wake up from the low power mode at a time to receive and decode at least a portion of the third beacon frame, in which the time to wake up is based on the expected time to receive the common bytes instead of based on an expected time to receive a preamble at a start of the third beacon frame.
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