US 11,800,249 B2
Imaging device for connection with a circuit element
Yuta Momiuchi, Kanagawa (JP); and Yuji Takaoka, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Jan. 3, 2022, as Appl. No. 17/646,751.
Application 17/646,751 is a continuation of application No. 16/972,862, granted, now 11,245,863, previously published as PCT/JP2019/014760, filed on Apr. 3, 2019.
Claims priority of application No. 2018-112742 (JP), filed on Jun. 13, 2018.
Prior Publication US 2022/0132059 A1, Apr. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 25/70 (2023.01); H01L 27/146 (2006.01); H04N 23/00 (2023.01); H04N 23/54 (2023.01); H04N 23/57 (2023.01); H04N 25/44 (2023.01); G03B 17/02 (2021.01); H05K 1/18 (2006.01); H05K 3/10 (2006.01)
CPC H04N 25/70 (2023.01) [G03B 17/02 (2013.01); H01L 27/146 (2013.01); H01L 27/14618 (2013.01); H01L 27/14636 (2013.01); H04N 23/00 (2023.01); H04N 23/54 (2023.01); H04N 23/57 (2023.01); H04N 25/44 (2023.01); H05K 1/185 (2013.01); H05K 3/103 (2013.01); H05K 2201/095 (2013.01); H05K 2201/09118 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An optical device, comprising:
a pixel formation surface;
an imaging element that includes:
a lens;
a pixel region on the pixel formation surface; and
a rewiring region, wherein
the rewiring region is in a first region, of the imaging element, different from the pixel region, and
the rewiring region includes a pad;
a mold part around the imaging element, wherein the mold part is in a second region, of the optical device, different from the pixel formation surface;
a rewiring layer on each of a pixel formation surface side of the imaging element and a pixel formation surface side of the mold part, wherein the rewiring layer is configured to connect an external terminal and the pad; and
a third region on the pixel formation surface side of the mold part, wherein
the third region is for arrangement of a circuit element to be connected to the rewiring layer, and
the external terminal corresponds to a terminal of the circuit element.