CPC H04L 1/0041 (2013.01) [H04L 1/0057 (2013.01); H04L 1/0067 (2013.01); H04L 1/0071 (2013.01); H04L 5/0007 (2013.01); H04L 5/0048 (2013.01)] | 20 Claims |
1. An apparatus for wireless communication, the apparatus comprising:
a processor; and
a memory coupled with the processor, the memory storing executable instructions that when executed by the processor cause the processor to effectuate operations comprising:
obtaining a physical broadcast channel (PBCH) payload, wherein the payload is generated by inserting at least 3 bits of a synchronization signal (SS) block timing index followed by a half frame indication bit;
scrambling the PBCH payload based on a first scrambler, the scrambled PBCH payload creating a first sequence, wherein the first scrambler indicates at least 2 bits of the SS block timing index;
polar encoding the first sequence to generate a first encoded sequence;
scrambling the first encoded sequence based on a second scrambler, the scrambled first encoded sequence creating a second encoded sequence;
generating a PBCH signal based on the second encoded sequence;
obtaining a demodulation reference signal (DMRS) sequence, wherein the DMRS sequence is generated by using a sequence generator initialized with the cell identifier and 2 or 3 least significant bits of the SS block timing index;
generating a DMRS based on the DMRS sequence; and
transmitting a SS block comprising the PBCH signal and the DMRS according to the SS block timing index.
|