US 11,799,427 B2
Amplifier capacitive load compensation
Vishnuvardhan Reddy Jaladanki, Secunderabad (IN); and Preetam Charan Anand Tadeparthy, Bengaluru (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Oct. 29, 2021, as Appl. No. 17/514,087.
Claims priority of application No. 202041049453 (IN), filed on Nov. 12, 2020.
Prior Publication US 2022/0149792 A1, May 12, 2022
Int. Cl. H03F 3/04 (2006.01); H02M 3/155 (2006.01); H03F 3/50 (2006.01); H03F 3/45 (2006.01); H03F 1/08 (2006.01)
CPC H03F 3/04 (2013.01) [H02M 3/155 (2013.01); H03F 1/086 (2013.01); H03F 3/45192 (2013.01); H03F 3/505 (2013.01); H03F 2203/45124 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An amplifier, comprising:
a first stage including:
an output;
a first compensation network coupled to the output of the first stage;
a second stage including:
a source follower including:
an input coupled to the output of the first stage; and
an output; and
a second compensation network coupled between the input of the source follower and the output of the source follower;
wherein:
the source follower includes a first transistor having:
a first current terminal coupled to a power supply terminal;
a second current terminal coupled to the second compensation network; and
a control terminal coupled to the output of the first stage; and
the second stage includes:
a second transistor including:
a first current terminal coupled to the first current terminal of the first transistor;
a control terminal coupled to the control terminal of the first transistor; and
a second current terminal; and
a current mirror circuit coupled to the second current terminal of the first transistor and the second current terminal of the second transistor, wherein the current mirror circuit includes:
a third transistor including:
a first current terminal coupled to the second current terminal of the first transistor;
a second current terminal coupled to ground; and
a control terminal; and
a fourth transistor including:
a first current terminal coupled to the second current terminal of the second transistor;
a control terminal coupled to the control terminal of the third transistor; and
a second current terminal coupled to the control terminal of the third transistor.