US 11,799,281 B2
Short circuit protection
Eung Jung Kim, Allen, TX (US); and Wenchao Qu, Plano, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Oct. 29, 2021, as Appl. No. 17/514,774.
Claims priority of provisional application 63/184,005, filed on May 4, 2021.
Prior Publication US 2022/0360068 A1, Nov. 10, 2022
Int. Cl. H02H 3/08 (2006.01); H02H 1/06 (2006.01)
CPC H02H 3/08 (2013.01) [H02H 1/06 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a power switch having a power switch source configured to receive an input voltage, a power switch drain, and a power switch gate;
a current sense component coupled to the power switch;
a current limiting circuit coupled to the power switch gate, the power switch drain, and the current sense component;
an over-current protection (OCP) circuit coupled to the power switch source, the power switch drain, and the power switch gate; and
an output voltage (VOUT) clamp coupled to the power switch drain and the power switch gate, wherein the VOUT clamp includes:
a bi-polar junction transistor (BJT) having a collector, an emitter, and a base, the base configured to receive a reference voltage, and the emitter coupled to the power switch drain,
a first field effect transistor (FET) having a first FET drain, a first FET gate, and a first FET source, the first FET gate coupled to the collector, and the first FET source coupled to the collector through a first resistor;
a second FET having a second FET drain, a second FET source, and a second FET gate, wherein the second FET drain and the second FET gate is coupled to the first FET drain, and the second FET source is coupled to a ground terminal;
a third FET having a third FET drain, a third FET source, and a third FET gate, wherein the third FET gate is coupled to the first FET drain, the third FET drain is coupled to the power switch gate, and the third FET source is coupled to the ground terminal; and
a fourth FET having a fourth FET drain, a fourth FET source, and a fourth FET gate, wherein the fourth FET gate is coupled to the collector, the fourth FET source is coupled to the collector through the first resistor, and the fourth FET drain is coupled to the ground terminal through a second resistor, wherein a negative output detection signal is provided at the fourth FET drain.