US 11,799,019 B2
Gate isolation feature and manufacturing method thereof
Kuan-Ting Pan, Hsinchu (TW); Huan-Chieh Su, Changhua County (TW); Jia-Chuan You, Taoyuan County (TW); Shi Ning Ju, Hsinchu (TW); Kuo-Cheng Chiang, Hsinchu County (TW); Yi-Ruei Jhan, Hsinchu (TW); Li-Yang Chuang, Hsinchu (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Nov. 6, 2020, as Appl. No. 17/91,767.
Claims priority of provisional application 62/982,149, filed on Feb. 27, 2020.
Prior Publication US 2021/0273075 A1, Sep. 2, 2021
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01)
CPC H01L 29/6681 (2013.01) [H01L 21/823431 (2013.01); H01L 29/0649 (2013.01); H01L 29/0669 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a plurality of fin structures extending along a first direction over a substrate;
a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures, wherein the dummy fin structures include a first dummy fin structure having a first sidewall, a second sidewall that opposes the first sidewall and a topmost surface extending from the first sidewall to the second sidewall;
a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments; and
a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures, wherein the cut feature physically contacts the first sidewall, the second sidewall and the topmost surface of the first dummy fin structure.