US 11,799,012 B2
Semiconductor device and method for fabricating the same
Chun-Chieh Chiu, Keelung (TW); Pin-Hong Chen, Tainan (TW); Yi-Wei Chen, Taichung (TW); Tsun-Min Cheng, Changhua County (TW); Chih-Chien Liu, Taipei (TW); Tzu-Chieh Chen, Pingtung County (TW); Chih-Chieh Tsai, Kaohsiung (TW); Kai-Jiun Chang, Taoyuan (TW); Yi-An Huang, New Taipei (TW); Chia-Chen Wu, Nantou County (TW); and Tzu-Hao Liu, Taichung (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW); and Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW); and Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Filed on Sep. 4, 2020, as Appl. No. 17/12,088.
Application 17/012,088 is a division of application No. 15/985,730, filed on May 22, 2018, granted, now 10,804,365.
Claims priority of application No. 201810337007.0 (CN), filed on Apr. 16, 2018.
Prior Publication US 2020/0403077 A1, Dec. 24, 2020
Int. Cl. H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 29/423 (2006.01); H10B 12/00 (2023.01); H01L 21/285 (2006.01)
CPC H01L 29/4941 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/28052 (2013.01); H01L 21/28061 (2013.01); H01L 21/3213 (2013.01); H01L 29/42372 (2013.01); H10B 12/05 (2023.02); H10B 12/482 (2023.02); H01L 21/28518 (2013.01); H01L 21/28556 (2013.01); H10B 12/30 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A method for fabricating semiconductor device, comprising:
forming a silicon layer on a substrate;
forming a metal silicon nitride layer on the silicon layer, wherein the metal silicon nitride layer comprises a bottom portion, a middle portion, and a top portion, a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion while the bottom portion, the middle portion, and the top portion comprise a same material, and a concentration of silicon in the bottom portion is greater than a concentration of silicon in the top portion;
forming a conductive layer on the metal silicon nitride layer; and
patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.