CPC H01L 29/4941 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/28052 (2013.01); H01L 21/28061 (2013.01); H01L 21/3213 (2013.01); H01L 29/42372 (2013.01); H10B 12/05 (2023.02); H10B 12/482 (2023.02); H01L 21/28518 (2013.01); H01L 21/28556 (2013.01); H10B 12/30 (2023.02)] | 9 Claims |
1. A method for fabricating semiconductor device, comprising:
forming a silicon layer on a substrate;
forming a metal silicon nitride layer on the silicon layer, wherein the metal silicon nitride layer comprises a bottom portion, a middle portion, and a top portion, a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion while the bottom portion, the middle portion, and the top portion comprise a same material, and a concentration of silicon in the bottom portion is greater than a concentration of silicon in the top portion;
forming a conductive layer on the metal silicon nitride layer; and
patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.
|