US 11,799,007 B2
Thicker corner of a gate dielectric structure around a recessed gate electrode for an MV device
Yi-Huan Chen, Hsin Chu (TW); Kong-Beng Thei, Pao-Shan Village (TW); Chien-Chih Chou, New Taipei (TW); Alexander Kalnitsky, San Francisco, CA (US); Szu-Hsien Liu, Zhubei (TW); and Huan-Chih Yuan, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 27, 2022, as Appl. No. 17/874,471.
Application 17/874,471 is a continuation of application No. 17/098,867, filed on Nov. 16, 2020, granted, now 11,469,307.
Claims priority of provisional application 63/084,682, filed on Sep. 29, 2020.
Prior Publication US 2022/0367654 A1, Nov. 17, 2022
Int. Cl. H01L 29/423 (2006.01); H01L 29/40 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/42368 (2013.01) [H01L 21/76224 (2013.01); H01L 21/823462 (2013.01); H01L 29/401 (2013.01); H01L 29/4236 (2013.01); H01L 29/7813 (2013.01); H01L 29/7825 (2013.01); H01L 29/7834 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first doped region arranged within a semiconductor substrate, the first doped region having a first doping conductivity;
a second doped region and a third doped region arranged within the semiconductor substrate on opposite sides of the first doped region, the second doped region and the third doped region having a second doping conductivity opposite the first doping conductivity;
a gate electrode arranged over the first doped region, the gate electrode comprising a bottom surface arranged below a topmost surface of the semiconductor substrate; and
a gate dielectric structure separating the gate electrode from the first doped region, wherein the gate dielectric structure comprises a central portion having a first thickness and a corner portion having a second thickness, and wherein the second thickness is at least two times greater than the first thickness; and
a trench isolation structure laterally surrounding the first doped region, the second doped region, and the third doped region, wherein the bottom surface of the gate electrode is below an upper surface of the trench isolation structure.