CPC H01L 29/41733 (2013.01) [H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
1. A method comprising:
depositing a dummy semiconductor layer and a first semiconductor layer over a substrate;
forming spacers on sidewalls of the dummy semiconductor layer;
forming a first epitaxial material and a second epitaxial material in the substrate;
exposing the dummy semiconductor layer and the first epitaxial material, wherein exposing the dummy semiconductor layer and the first epitaxial material comprises thinning a backside of the substrate;
etching the dummy semiconductor layer to expose the first semiconductor layer, wherein the spacers remain over and in contact with end portions of the first semiconductor layer while etching the dummy semiconductor layer;
etching portions of the first semiconductor layer using the spacers as a mask; and
replacing the second epitaxial material and the first epitaxial material with a backside via, the backside via being electrically coupled to a source/drain region of a first transistor.
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