US 11,799,001 B2
Back-end-of-line devices
Yu-Hsiang Chen, Hsinchu (TW); Po-Hsiang Huang, Taipei (TW); Wen-Sheh Huang, Hsin Chu (TW); Hsing-Leo Tsai, Hsinchu (TW); and Chia-En Huang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 21, 2021, as Appl. No. 17/327,341.
Claims priority of provisional application 63/158,459, filed on Mar. 9, 2021.
Prior Publication US 2022/0293749 A1, Sep. 15, 2022
Int. Cl. H01L 29/41 (2006.01); H01L 29/417 (2006.01); H01L 21/48 (2006.01); H01L 23/522 (2006.01)
CPC H01L 29/41725 (2013.01) [H01L 21/486 (2013.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a transistor; and
an interconnect structure disposed over the transistor, wherein the interconnect structure comprises:
a first dielectric layer,
a first conductive feature in the first dielectric layer,
a first etch stop layer (ESL) disposed on a top surface of the first dielectric layer,
a dielectric feature disposed in the first ESL and in contact with a top surface of the first conductive feature and the top surface of the first dielectric layer,
an electrode disposed over the dielectric feature such that the electrode is vertically spaced apart from the top surface of the first conductive feature by the dielectric feature, and
a second ESL disposed on and in contact with top surfaces of the dielectric feature and the electrode.