US 11,798,979 B2
Integrated capacitor with sidewall having reduced roughness
Elizabeth Costner Stewart, Dallas, TX (US); Jeffrey A. West, Dallas, TX (US); Thomas D. Bonifield, Dallas, TX (US); Joseph Andre Gallegos, Dallas, TX (US); Jay Sung Chun, Plano, TX (US); and Zhiyi Yu, Allen, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jan. 25, 2021, as Appl. No. 17/156,793.
Application 17/156,793 is a division of application No. 15/348,580, filed on Nov. 10, 2016, granted, now 10,978,548.
Prior Publication US 2021/0143249 A1, May 13, 2021
Int. Cl. H01L 49/02 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01)
CPC H01L 28/40 (2013.01) [H01L 21/02211 (2013.01); H01L 21/02214 (2013.01); H01L 21/02216 (2013.01); H01L 21/02263 (2013.01); H01L 21/02274 (2013.01); H01L 21/31116 (2013.01); H01L 21/7682 (2013.01); H01L 21/76822 (2013.01); H01L 21/76825 (2013.01); H01L 21/76837 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An integrated capacitor, comprising:
a semiconductor surface on a substrate;
a bottom plate above and electrically isolated from said semiconductor surface;
a dielectric feature comprising at least one silicon compound material layer having a sloped dielectric sidewall portion on said bottom plate;
a discontinuous dielectric layer, including noncontiguous dielectric portions, that at least partially fills pits on a surface of said sloped dielectric sidewall portion, said discontinuous dielectric layer having an interface with said sloped dielectric sidewall portion, and
a top plate on a top of said dielectric feature.