US 11,798,945 B2
Semiconductor structure
Winnie Victoria Wei-Ning Chen, Zhubei (TW); Meng-Hsuan Hsiao, Hsinchu (TW); Tung-Ying Lee, Hsinchu (TW); Pang-Yen Tsai, Jhu-bei (TW); and Yasutoshi Okuno, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 22, 2022, as Appl. No. 17/846,543.
Application 16/910,297 is a division of application No. 15/963,920, filed on Apr. 26, 2018, granted, now 10,700,066, issued on Jun. 30, 2020.
Application 17/846,543 is a continuation of application No. 17/140,289, filed on Jan. 4, 2021.
Application 17/140,289 is a continuation of application No. 16/910,297, filed on Jun. 24, 2020, granted, now 10,886,270, issued on Jan. 5, 2021.
Claims priority of provisional application 62/593,143, filed on Nov. 30, 2017.
Prior Publication US 2022/0328480 A1, Oct. 13, 2022
Int. Cl. H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 21/306 (2006.01); H01L 29/16 (2006.01); H01L 21/02 (2006.01); H01L 29/10 (2006.01); H01L 21/8238 (2006.01)
CPC H01L 27/092 (2013.01) [H01L 21/02636 (2013.01); H01L 21/30625 (2013.01); H01L 21/823807 (2013.01); H01L 29/0673 (2013.01); H01L 29/0676 (2013.01); H01L 29/1033 (2013.01); H01L 29/16 (2013.01); H01L 29/42392 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a semiconductor layer formed over the substrate;
a first channel layer and a second channel layer vertically stacked over the semiconductor layer;
a first insulating structure interposing the first channel layer and the semiconductor layer;
a second insulating structure interposing the first channel layer and the second channel layer;
a gate stack abutting the first channel layer and the second channel layer, wherein the gate stack comprises:
a first portion vertically sandwiched between the first channel layer and the semiconductor layer; and
a second portion vertically sandwiched between the first channel layer and the second channel layer,
wherein a first distance between two opposite edges of the first portion of the gate stack is different from a second distance between two opposite edges of the second portion of the gate stack; and
a source/drain region having a first region attached to the first insulating structure and a second region attached to the second insulating structure, wherein a third distance between two opposite edges of the first region is different from a fourth distance between two opposite edges of the second region.