US 11,798,944 B2
Integration of silicon channel nanostructures and silicon-germanium channel nanostructures
Shi Ning Ju, Hsinchu (TW); Kuo-Cheng Chiang, Zhubei (TW); Chih-Hao Wang, Baoshan Township (TW); Kuan-Lun Cheng, Hsinchu (TW); and Guan-Lin Chen, Baoshan Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Apr. 4, 2022, as Appl. No. 17/712,255.
Application 17/712,255 is a continuation of application No. 16/910,488, filed on Jun. 24, 2020, granted, now 11,296,081.
Prior Publication US 2022/0231017 A1, Jul. 21, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/088 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 29/0653 (2013.01); H01L 29/0665 (2013.01); H01L 29/16 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a first gate-all-around field effect transistor located over a substrate and comprising:
at least one silicon portion comprising a middle portion, a first end and a second end;
a first gate structure including a first gate dielectric layer and a first gate electrode and surrounding each middle portion of the at least one silicon portion;
a first source region located on a first end of the at least one silicon portion; and
a first drain region located on a second end of the at least one silicon portion; and
a second gate-all-around field effect transistor located over the substrate, laterally spaced from the first gate-all-around field effect transistor, and comprising:
at least one silicon-germanium portion;
a second gate structure including a second gate dielectric layer and a second gate electrode and surrounding each middle portion of the at least one silicon-germanium portion;
a second source region located on a first end of the at least one silicon-germanium portion; and
a second drain region located on a second end of the at least one silicon-germanium portion,
wherein:
each of the at least one silicon portion and each of the at least one silicon-germanium portion is single crystalline; and
each crystallographic orientation having a same Miller index is orientated along a same direction as the at least one silicon portion and the at least one silicon-germanium portion.