US 11,798,942 B2
Methods of manufacturing semiconductor devices having fins and an isolation region
Chia-Sheng Fan, Zhubei (TW); Bao-Ru Young, Zhubei (TW); and Tung-Heng Hsieh, Zhudong Town (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 26, 2021, as Appl. No. 17/240,673.
Application 17/240,673 is a division of application No. 16/722,271, filed on Dec. 20, 2019, granted, now 10,991,691.
Application 16/050,553 is a division of application No. 15/581,565, filed on Apr. 28, 2017, granted, now 10,354,997, issued on Jul. 16, 2019.
Application 16/722,271 is a continuation of application No. 16/050,553, filed on Jul. 31, 2018, granted, now 10,515,957, issued on Dec. 24, 2019.
Prior Publication US 2021/0249409 A1, Aug. 12, 2021
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/0217 (2013.01); H01L 21/0223 (2013.01); H01L 21/02255 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/42376 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 21/823828 (2013.01); H01L 21/823878 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first fin and a second fin extending from a substrate;
forming a dummy gate dielectric on the first fin and the second fin;
forming a dummy gate electrode on the dummy gate dielectric;
patterning an opening in the dummy gate electrode and the dummy gate dielectric, the opening disposed between the first fin and the second fin;
oxidizing sidewalls of the dummy gate electrode to form sacrificial oxides in the opening;
forming a first isolation region between the sacrificial oxides in the opening;
removing the dummy gate electrode with a first etch; and
after removing the dummy gate electrode, removing the dummy gate dielectric and the sacrificial oxides with a second etch, the second etch being selective to materials of the dummy gate dielectric and the sacrificial oxides.