US 11,798,846 B2
Contact plug
Chih-Hsuan Lin, Hsinchu (TW); Xi-Zong Chen, Tainan (TW); and Chih-Teng Liao, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 6, 2021, as Appl. No. 17/142,750.
Claims priority of provisional application 63/071,194, filed on Aug. 27, 2020.
Claims priority of provisional application 63/065,630, filed on Aug. 14, 2020.
Prior Publication US 2022/0051940 A1, Feb. 17, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 21/285 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 21/28518 (2013.01); H01L 21/7685 (2013.01); H01L 21/76829 (2013.01); H01L 21/76846 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a gate structure;
a source/drain feature adjacent the gate structure;
a contact etch stop layer (CESL) over the source/drain feature;
a first dielectric layer over the CESL;
an etch stop layer over the gate structure, the CESL and the first dielectric layer;
a second dielectric layer over the etch stop layer;
a source/drain contact comprising:
a first portion extending through the first dielectric layer and the CESL, and
a second portion extending through the etch stop layer and the second dielectric layer;
a metal silicide layer disposed between the second portion and etch stop layer;
a metal nitride layer disposed between the first portion and the first dielectric layer as well as between the first portion and the CESL,
wherein a portion of a sidewall of the first portion is spaced apart from the CESL by the first dielectric layer.