US 11,798,843 B2
Conductive feature formation and structure
Yu Shih Wang, Tainan (TW); Chun-I Tsai, Hsinchu (TW); Shian Wei Mao, Taipei (TW); Ken-Yu Chang, Hsinchu (TW); Ming-Hsing Tsai, Chu-Pei (TW); and Wei-Jung Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 5, 2021, as Appl. No. 17/221,958.
Application 16/203,918 is a division of application No. 15/880,448, filed on Jan. 25, 2018, granted, now 10,361,120, issued on Jul. 23, 2019.
Application 17/221,958 is a continuation of application No. 16/203,918, filed on Nov. 29, 2018, granted, now 10,971,396.
Claims priority of provisional application 62/592,476, filed on Nov. 30, 2017.
Prior Publication US 2021/0225701 A1, Jul. 22, 2021
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 21/3213 (2006.01); H01L 23/485 (2006.01)
CPC H01L 21/76847 (2013.01) [H01L 21/32134 (2013.01); H01L 21/76846 (2013.01); H01L 23/485 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53252 (2013.01); H01L 23/53266 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a dielectric layer over a conductive feature, the dielectric layer being a single dielectric layer, the dielectric layer having a sidewall;
a conductive layer in the dielectric layer, the conductive layer being in electrical contact with the conductive feature, wherein an upper surface of the conductive layer is level with an upper surface of the dielectric layer;
a barrier layer interposed between the conductive layer and the dielectric layer along a line parallel to the upper surface of the dielectric layer, an upper surface of the barrier layer being covered by the conductive layer, wherein a thickness of an upper portion of the barrier layer is less than a thickness of a lower portion of the barrier layer, wherein the barrier layer is a conductive material;
an adhesion layer interposed between the barrier layer and the dielectric layer; and
a gate structure and a spacer adjacent the gate structure, wherein a surface of the adhesion layer contacts a surface of the spacer.