US 11,798,836 B2
Semiconductor isolation structure and method of making the same
Tsung-Yu Yang, Hsinchu (TW); Po-Wei Liu, Hsinchu (TW); Yun-Chi Wu, Hsinchu (TW); Yu-Wen Tseng, Hsinchu (TW); Chia-Ta Hsieh, Hsinchu (TW); Ping-Cheng Li, Hsinchu (TW); Tsung-Hua Yang, Hsinchu (TW); and Yu-Chun Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 17, 2021, as Appl. No. 17/350,930.
Prior Publication US 2022/0406652 A1, Dec. 22, 2022
Int. Cl. H01L 21/762 (2006.01); H01L 21/74 (2006.01); H01L 23/535 (2006.01)
CPC H01L 21/76283 (2013.01) [H01L 21/743 (2013.01); H01L 23/535 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor isolation structure comprising:
a silicon-on-insulator substrate including
a semiconductor substrate,
a buried insulation layer disposed on the semiconductor substrate, and
a semiconductor layer disposed on the buried insulation layer, and having a functional region;
a first deep trench isolation structure penetrating the semiconductor layer and the buried insulation layer, and surrounding the functional region;
a second deep trench isolation structure penetrating the semiconductor layer and the buried insulation layer, and surrounding the first deep trench isolation structure; and
a shallow trench isolation structure formed in the semiconductor layer and surrounding the functional region, the shallow trench isolation structure including a first shallow trench isolation that surrounds the functional region, and a second shallow trench isolation that surrounds the first shallow trench isolation, the first and second deep trench isolation structures respectively penetrating the first and second shallow trench isolations.