US 11,798,812 B2
Landing metal etch process for improved overlay control
Chih-Min Hsiao, Taoyuan (TW); Chih-Ming Lai, Hsinchu (TW); Chien-Wen Lai, Hsinchu (TW); Ya Hui Chang, Hsinchu (TW); and Ru-Gun Liu, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on May 2, 2022, as Appl. No. 17/735,073.
Application 17/735,073 is a division of application No. 16/688,681, filed on Nov. 19, 2019, granted, now 11,322,362, issued on May 3, 2022.
Claims priority of provisional application 62/774,125, filed on Nov. 30, 2018.
Prior Publication US 2022/0262647 A1, Aug. 18, 2022
Int. Cl. H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01)
CPC H01L 21/31144 (2013.01) [H01L 21/76808 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
an insulating layer;
a via recess in the insulating layer;
a hard mask layer over an upper surface of the insulating layer and having an opening over the via recess such that portions of the upper surface of the insulating layer are exposed via the opening;
metal formed in the via recess, in the opening, and on the exposed upper surface of the insulating layer; and
a metal line over the via recess and in contact with the metal in the opening, wherein an axis of the metal line is offset from the center of the via recess.