CPC H01L 21/28185 (2013.01) [H01L 21/823456 (2013.01); H01L 21/823462 (2013.01); H01L 27/088 (2013.01); H01L 29/42376 (2013.01)] | 20 Claims |
1. A method of manufacturing a semiconductor device, the method comprising:
depositing a first dielectric layer over a logic region and an analog region of a semiconductor substrate;
treating the first dielectric layer to form a recovered layer and a non-treated layer, the non-treated layer being located between the recovered layer and the semiconductor substrate;
after the treating the first dielectric layer, removing a first portion of the recovered layer from the logic region while the non-treated layer is present;
forming a second dielectric layer in the logic region; and
depositing a gate electrode material over a remainder of the recovered layer and the second dielectric layer.
|