US 11,798,746 B2
Multilayer ceramic capacitor
Hideaki Tanaka, Nagaokakyo (JP); Daiki Fukunaga, Nagaokakyo (JP); and Koji Moriyama, Nagaokakyo (JP)
Assigned to MURATA MANUFACTURING CO., LTD., Kyoto (JP)
Filed by Murata Manufacturing Co., Ltd., Nagaokakyo (JP)
Filed on Mar. 17, 2021, as Appl. No. 17/203,846.
Application 17/203,846 is a continuation of application No. 16/793,041, filed on Feb. 18, 2020, granted, now 11,120,945.
Application 16/793,041 is a continuation of application No. 16/568,573, filed on Sep. 12, 2019, granted, now 10,720,281, issued on Jul. 21, 2020.
Application 16/568,573 is a continuation of application No. 16/285,286, filed on Feb. 26, 2019, granted, now 10,600,575, issued on Mar. 24, 2020.
Application 16/285,286 is a continuation of application No. 16/208,924, filed on Dec. 4, 2018, granted, now 10,410,791, issued on Sep. 10, 2019.
Application 16/208,924 is a continuation of application No. 15/960,694, filed on Apr. 24, 2018, granted, now 10,325,726, issued on Jun. 18, 2019.
Application 15/960,694 is a continuation of application No. 15/210,933, filed on Jul. 15, 2016, granted, now 9,984,824, issued on May 29, 2018.
Claims priority of application No. 2015-142975 (JP), filed on Jul. 17, 2015.
Prior Publication US 2021/0202182 A1, Jul. 1, 2021
Int. Cl. H01G 4/005 (2006.01); H01G 4/232 (2006.01); H01G 4/30 (2006.01); H01G 4/12 (2006.01)
CPC H01G 4/30 (2013.01) [H01G 4/005 (2013.01); H01G 4/232 (2013.01); H01G 4/1218 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A multilayer ceramic capacitor comprising:
a laminated body including a plurality of dielectric layers and a plurality of internal electrodes laminated in a lamination direction; and
a plurality of external electrodes electrically connected to respective ones of the internal electrodes; wherein
the laminated body includes a first principal surface and a second principal surface opposed in the lamination direction, a first side surface and a second side surface opposed in a width direction perpendicular or substantially perpendicular to the lamination direction, and a first end surface and a second end surface opposed in a length direction perpendicular or substantially perpendicular to both the lamination direction and the width direction;
the plurality of internal electrodes include first internal electrodes exposed at the first end surface, and second internal electrodes exposed at the second end surface;
the laminated body includes outer layer portions provided at a top and a bottom of the laminated body in the lamination direction, and an inner layer portion between the outer layer portions;
the plurality of external electrodes include a first external electrode covering the first end surface and electrically connected to the first internal electrodes, and a second external electrode covering the second end surface and electrically connected to the second internal electrodes;
each of the first external electrode and the second external electrode includes a multilayer structure including a base electrode layer, a conductive resin layer on the base electrode layer, and a plating layer on the conductive resin layer;
side margin portions sandwich the plurality of dielectric layers in the width direction;
each of the side margin portions includes Si; and
in at least one cross sectional view in the width and lamination directions, the Si is included in a plurality of Si segregation portions in at least one of the side margin portions.